A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Partial scan flip-flop selection by use of empirical testability
Journal of Electronic Testing: Theory and Applications - Special issue on partial scan methods
Testability-based partial scan analysis
Journal of Electronic Testing: Theory and Applications - Special issue on partial scan methods
Exploiting hardware sharing in high-level synthesis for partial scan optimization
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
High-level variable selection for partial-scan implementation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Full scan fault coverage with partial scan
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Art of Software Testing
Observability analysis of embedded software for coverage-directed validation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Designing Circuits with Partial Scan
IEEE Design & Test
A Global Algorithm for the Partial Scan Design Problem Using Circuit State Information
Proceedings of the IEEE International Test Conference on Test and Design Validity
Partial Scan Flip Flop Selection for Simulation-Based Sequential ATPGs
Proceedings of the IEEE International Test Conference on Test and Design Validity
Partial Scan High-Level Synthesis
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Partial Scan Selection Based on Dynamic Reachability and Observability Information
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Scan design has been widely used to ease test generation process for digital circuits. Although full scan approach results in high fault coverage while reducing ATPG effort, it introduces area and performance overheads that are most times unacceptable. Hence, partial scan is a commonly used technique to improve testability of sequential circuits while respecting design constraints. In this paper, we present a method to select sequential elements (flip-flops) to compose a partial scan chain. We use a software engineering technique to identify internal variables or signals of the circuit's behavioral description that have low observability. Experiments demonstrate that our approach achieves a high fault coverage including few flip-flops in the scan chain. Moreover, comparative results show that, for complex circuits, proposed technique is more efficient than some classical methods in selecting flip-flops to compose partial scan.