Full scan fault coverage with partial scan
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Formal Value-Range and Variable Testability Techniquesfor High-Level Design-For-Testability
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Behavioral-Level DFT via Formal Operator Testability Measures
Journal of Electronic Testing: Theory and Applications
Partial Scan Using Multi-Hop State Reachability Analysis
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Partial Scan Design Based on Circuit State Information and Functional Analysis
IEEE Transactions on Computers
Using a software testing technique to identify registers for partial scan implementation
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Eliminating the Timing Penalty of Scan
Journal of Electronic Testing: Theory and Applications
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A partial scan selection strategy is proposed in which flip-flops are selected via newly proposed dynamic reachability and observability measures such that the remaining hard-to-detect faults are easily detected. This is done by taking advantage of the information available when a target fault is aborted by the test generator. A partial scan selection tool, IDROPS, has been developed which selects the best and smallest set of flip-flops to scan that will result in a high fault coverage. Results indicate that high fault coverage in hard-to-test circuits can be achieved using fewer scan flip-flops than in previous methods.