A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
A cost-based approach to partial scan
DAC '93 Proceedings of the 30th international Design Automation Conference
Implicit computation of minimum-cost feedback-vertex sets for partial scan and other applications
DAC '94 Proceedings of the 31st annual Design Automation Conference
An exact algorithm for selecting partial scan flip-flops
DAC '94 Proceedings of the 31st annual Design Automation Conference
Partial scan flip-flop selection by use of empirical testability
Journal of Electronic Testing: Theory and Applications - Special issue on partial scan methods
Testability-based partial scan analysis
Journal of Electronic Testing: Theory and Applications - Special issue on partial scan methods
An optimal algorithm for cycle breaking in directed graphs
Journal of Electronic Testing: Theory and Applications - Special issue on partial scan methods
A three-stage partial scan design method to ease ATPG
Journal of Electronic Testing: Theory and Applications - Special issue on partial scan methods
Exploiting symbolic techniques for partial scan flip flop selection
Proceedings of the conference on Design, automation and test in Europe
A New Method for Partial Scan Design Based on Propagation and Justification Requirements of Faults
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Partial Scan Design Based on State Transition Modeling
Proceedings of the IEEE International Test Conference on Test and Design Validity
A Global Algorithm for the Partial Scan Design Problem Using Circuit State Information
Proceedings of the IEEE International Test Conference on Test and Design Validity
Partial Scan Flip Flop Selection for Simulation-Based Sequential ATPGs
Proceedings of the IEEE International Test Conference on Test and Design Validity
A comprehensive approach to the partial scan problem using implicit state enumeration
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Sequential Circuit Test Generation Using Dynamic State Traversal
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Partial Scan Selection Based on Dynamic Reachability and Observability Information
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
An incomplete scan design approach to test generation for sequential machines
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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Sequential test generators fail to yield tests for some stuck-at-faults because they are unable to reach certain states necessary for exciting/propagating these target faults. Adding scan to the circuit increases reachability of these hard- to-reach and/or previously unreachable states. In this paper, we postulated that fewer scan ip- ops are needed to make these states reachable. The states necessary for detecting the hard-to-detect faults, when reached, will facilitate reaching other hard-to-reach states in one or more hops by the sequential test generator, resulting in significantly higher fault coverage. We collect information on the hard-to-reach, aborted, and easy states in our analysis. Results from our approach have indicated that higher fault coverage can be achieved with significantly fewer scan ip- ops for some circuits.