Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Partial scan design based on circuit state information
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Identification of unsettable flip-flops for partial scan and faster ATPG
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Partial Scan Design Based on State Transition Modeling
Proceedings of the IEEE International Test Conference on Test and Design Validity
A Global Algorithm for the Partial Scan Design Problem Using Circuit State Information
Proceedings of the IEEE International Test Conference on Test and Design Validity
A distance reduction approach to design for testability
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Improving topological ATPG with symbolic techniques
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Deterministic BIST with Partial Scan
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Partial Scan Using Multi-Hop State Reachability Analysis
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Partial Scan Design Based on Circuit State Information and Functional Analysis
IEEE Transactions on Computers
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Partial Scan techniques have been widely accepted as an effective solution to improve sequential ATPG performance while keeping acceptable area and performance overheads. Several techniques for flip-flop selection based on structural analysis have been presented in the literature. In this paper, we first propose a new testability measure based on the analysis of the circuit State Transition Graph through symbolic techniques. We then describe a scan flip flop selection algorithm exploiting this measure. We resort to the identification of several circuit macros to address large sequential circuits. When compared to other techniques, our approach shows good results, especially when it is used to optimize a set of flip-flops previously selected by means of structural analysis.