The Ballast Methodology for Structured Partial Scan Design
IEEE Transactions on Computers
A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
An analytical approach to the partial scan problem
Journal of Electronic Testing: Theory and Applications
An exact algorithm for selecting partial scan flip-flops
DAC '94 Proceedings of the 31st annual Design Automation Conference
Pattern generation for a deterministic BIST scheme
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Exploiting symbolic techniques for partial scan flip flop selection
Proceedings of the conference on Design, automation and test in Europe
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
A Global Algorithm for the Partial Scan Design Problem Using Circuit State Information
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Using BIST Control for Pattern Generation
Proceedings of the IEEE International Test Conference
Deterministic BIST with multiple scan chains
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Modeling Fault Coverage of Random Test Patterns
Journal of Electronic Testing: Theory and Applications
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An efficient deterministic BIST scheme based onpartial scan chains together with a scan selection algorithm tailoredfor BIST is presented. The algorithm determines a minimum number offlipflops to be scannable so that the remaining circuit has apipeline-like structure. Experiments show that scanning lessflipflops may even decrease the hardware overhead for the on-chippattern generator besides the classical advantages of partial scansuch as less impact on the system performance and less hardwareoverhead.