A Global Algorithm for the Partial Scan Design Problem Using Circuit State Information

Full scan fault coverage with partial scan

DATE '99 Proceedings of the conference on Design, automation and test in Europe

Deterministic BIST with Partial Scan

Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999

A Non-Scan Approach to DFT for Controllers Achieving 100% Fault Efficiency

Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98

Exploiting symbolic techniques for partial scan flip flop selection

Proceedings of the conference on Design, automation and test in Europe

Partial Scan Using Multi-Hop State Reachability Analysis

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium

Non-Scan Design for Testability for Synchronous Sequential Circuits Based on Conflict Analysis

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution

IEEE Transactions on Computers

Partial Scan Design Based on Circuit State Information and Functional Analysis

IEEE Transactions on Computers

Using a software testing technique to identify registers for partial scan implementation

SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design

Eliminating the Timing Penalty of Scan

Journal of Electronic Testing: Theory and Applications