The Ballast Methodology for Structured Partial Scan Design
IEEE Transactions on Computers
A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
An analytical approach to the partial scan problem
Journal of Electronic Testing: Theory and Applications
Implicit computation of minimum-cost feedback-vertex sets for partial scan and other applications
DAC '94 Proceedings of the 31st annual Design Automation Conference
An exact algorithm for selecting partial scan flip-flops
DAC '94 Proceedings of the 31st annual Design Automation Conference
Resynthesis and retiming for optimum partial scan
DAC '94 Proceedings of the 31st annual Design Automation Conference
Testability-based partial scan analysis
Journal of Electronic Testing: Theory and Applications - Special issue on partial scan methods
IEEE Transactions on Computers
Partial scan design based on circuit state information
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Full scan fault coverage with partial scan
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Timing analysis and optimization of sequential circuits
Timing analysis and optimization of sequential circuits
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Designing Circuits with Partial Scan
IEEE Design & Test
IEEE Design & Test
A New Method for Partial Scan Design Based on Propagation and Justification Requirements of Faults
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Partial Scan Design Based on State Transition Modeling
Proceedings of the IEEE International Test Conference on Test and Design Validity
A Global Algorithm for the Partial Scan Design Problem Using Circuit State Information
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
ATS '99 Proceedings of the 8th Asian Test Symposium
Test sequence compaction by reduced scan shift and retiming
ATS '95 Proceedings of the 4th Asian Test Symposium
Partial Scan beyond Cycle Cutting
FTCS '97 Proceedings of the 27th International Symposium on Fault-Tolerant Computing (FTCS '97)
Partial Scan Selection Based on Dynamic Reachability and Observability Information
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Combination of Structural and State Analysis for Partial Scan
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Partial Scan Design Based on Circuit State Information and Functional Analysis
IEEE Transactions on Computers
Eliminating Performance Penalty of Scan
VLSID '12 Proceedings of the 2012 25th International Conference on VLSI Design
A comprehensive approach to the partial scan problem using implicit state enumeration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Retiming scan circuit to eliminate timing penalty
LATW '12 Proceedings of the 2012 13th Latin American Test Workshop - LATW
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Stringent performance requirements magnify the performance degradation impact of Design-for-Testability (DfT) techniques. As more aggressive performance optimizations are being employed, resulting in high-performance designs with reduced logic depth, the impact of scan multiplexers is becoming even more magnified. In this work, we propose a pair of scan cell transformation techniques that transfers the scan multiplexer delay from the input of the flip-flop to its output, enabling the removal of the scan multiplexer delay off the critical paths. The first technique is an ad-hoc technique, while the second one is the retiming technique applied on the scan logic. The proposed transformation techniques retain the test development (test data, quality, etc.) and application (test time, power dissipation, etc.) intact, fully complying with the conventional design and test flow. Experimental results justify the efficacy of the proposed techniques in eliminating the performance penalty of scan in a cost-effective way and thus enhancing the functional speed of integrated circuits.