Implicit computation of minimum-cost feedback-vertex sets for partial scan and other applications

Selecting partial scan flip-flops for circuit partitioning

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

An exact algorithm for selecting partial scan flip-flops

DAC '94 Proceedings of the 31st annual Design Automation Conference

Partial scan with pre-selected scan signals

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Cost-free scan: a low-overhead scan path design methodology

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Oscillation control in logic simulation using dynamic dominance graphs

DAC '96 Proceedings of the 33rd annual Design Automation Conference

Partial Scan with Preselected Scan Signals

IEEE Transactions on Computers

Partial Scan Testing on the Register-Transfer Level

Journal of Electronic Testing: Theory and Applications

Partial Scan Using Multi-Hop State Reachability Analysis

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium

A synthesis-for-transparency approach for hierarchical and system-on-a-chip test

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Partial Scan Design Based on Circuit State Information and Functional Analysis

IEEE Transactions on Computers

Efficient multiple-bit retention register assignment for power gated design: concept and algorithms

Proceedings of the International Conference on Computer-Aided Design

Eliminating the Timing Penalty of Scan

Journal of Electronic Testing: Theory and Applications