Implicit computation of minimum-cost feedback-vertex sets for partial scan and other applications
DAC '94 Proceedings of the 31st annual Design Automation Conference
Benefits and Costs of Power-Gating Technique
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Power-gating-aware high-level synthesis
Proceedings of the 13th international symposium on Low power electronics and design
Low Power Methodology Manual: For System-on-Chip Design
Low Power Methodology Manual: For System-on-Chip Design
Scan based methodology for reliable state retention power gating designs
Proceedings of the Conference on Design, Automation and Test in Europe
Selective state retention design using symbolic simulation
Proceedings of the Conference on Design, Automation and Test in Europe
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Retention registers have been widely used in power gated design to store data during sleep mode. Since they consume much larger area and power than normal registers, it is imperative to minimize the total retention storage size. The current industry practice only replace all registers with single-bit retention ones, which significantly limits the design freedom and results in excessive area and power overhead. Towards this, for the first time in literature, we propose the concept of multi-bit retention register, with which only selected registers need to be replaced. It can significantly reduce the number of bits that need to be stored and thus the area and leakage power, but needs several clock cycles for mode transition. In addition, an efficient assignment algorithm is developed to minimize the total retention storage size subject to mode transition latency constraint. Experimental results show that our framework on average can reduce the leakage power in sleep mode and the retention storage area by 66.03%, compared with the single-bit retention register based design.