Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Implicit computation of minimum-cost feedback-vertex sets for partial scan and other applications
DAC '94 Proceedings of the 31st annual Design Automation Conference
An exact algorithm for selecting partial scan flip-flops
DAC '94 Proceedings of the 31st annual Design Automation Conference
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
On Synthesizing Circuits With Implicit Testability Constraints
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Test point insertion: scan paths through combinational logic
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
An RTL Methodology to Enable Low Overhead Combinational Testing
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Sequential Circuits with combinational Test Generation Complexity
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
High-Level Synthesis for Orthogonal Scan
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
H-SCAN+: A Practical Low-Overhead RTL Design-for-Testability Technique for Industrial Designs
ITC '97 Proceedings of the 1997 IEEE International Test Conference
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Conventional scan design imposes considerable area and delay overhead by using larger scan flip-flops and additional scan wires without utilizing the functionality of the combinational logic. We propose a novel low-overhead scan design methodology, called cost-free scan, which exploits the controllability of primary inputs to establish scan paths through the combinational logic. The methodology aims at reducing scan overhead by (1) analyzing the circuit to determine all the cost-free scan flip-flops, and (2) selecting the best primary input vector to establish the maximum number of cost-free scan flip-flops on the scan chain. Significant reduction in the scan overhead is achieved on ISCAS89 benchmarks, where in full scan environment, as many as 89% of the total flip-flops are found cost-free scannable, while in partial scan environment, reduction can be as high as 97% in scan flip-flops needed to break sequential loops.