COMPCON '92 Proceedings of the thirty-seventh international conference on COMPCON
Cost-free scan: a low-overhead scan path design methodology
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Orthogonal Scan: Low-Overhead Scan for Data Paths
Proceedings of the IEEE International Test Conference on Test and Design Validity
Synthesis-for-scan and scan chain ordering
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
A non-scan DFT method at register-transfer level to achieve complete fault efficiency
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Register-transfer level functional scan for hierarchical designs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A DFT method for time expansion model at register transfer level
Proceedings of the 44th annual Design Automation Conference
High-level test synthesis with hierarchical test generation for delay-fault testability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A graph-based approach to optimal scan chain stitching using RTL design descriptions
VLSI Design - Special issue on New Algorithmic Techniques for Complex EDA Problems
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Scan paths are commonly used in digital design to improve the testability of sequential circuits since a full scan path provides complete controllability and observability for every bistable element. A traditional scan path is implemented after the circuit has been designed, with little regard to the actual circuit function. High-level synthesis can exploit knowledge of the circuit function to synthesize a scannable circuit that has less area overhead than a circuit that has scan inserted after synthesis. In this paper, we discuss how synthesis algorithms that target orthogonal scan can result in final designs that are fully scanned and have as little as one-third the overhead of a traditional scan path.