Non-scan design-for-testability of RT-level data paths
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient algorithm to integrated scheduling and allocation in high-level test synthesis
Proceedings of the conference on Design, automation and test in Europe
A non-scan DFT method at register-transfer level to achieve complete fault efficiency
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Behavioral Synthesis for Easy Testability in Data Path Allocation
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Proceedings of the IEEE International Test Conference 2001
High-Level Synthesis for Orthogonal Scan
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
An optimized BIST test pattern generator for delay testing
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
15.2 Low Cost Partial Scan Design: A High Level Synthesis Approach
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Design for Hierarchical Two-Pattern Testability of Data Paths
ATS '01 Proceedings of the 10th Asian Test Symposium
A Multiple Phase Partial Scan Design Method
ATS '01 Proceedings of the 10th Asian Test Symposium
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Functional Illinois Scan Design at RTL
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
At-Speed Transition Fault Testing With Low Speed Scan Enable
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Design for Testability Based on Single-Port-Change Delay Testing for Data Paths
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
Multi-Cycle Sensitizable Transition Delay Faults
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Low Cost Launch-on-Shift Delay Test with Slow Scan Enable
ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On improving test quality of scan-based BIST
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Addressing design for testability at the architectural level
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A high-level test synthesis (HLTS) method targeted for delay-fault testability is presented in this paper. The proposed method, when combined with hierarchical test-pattern generation for embedded modules, guarantees a 100% delay test coverage for detectable faults in modules. A study on the delay testability problem in behavior level shows that low delay-fault coverage is usually attributed to the fact that a two-pattern test for delay testing cannot be delivered to modules under test in two consecutive cycles. To solve the problem, we propose an HLTS method that ensures that valid test pairs can be sent to each module through synthesized circuit hierarchy. Experimental results show that this method achieves 100% fault coverage for transition faults in modules; in contrast, the fault coverage in circuits synthesized by a left-edge-algorithm-based allocation algorithm is rather poor. The area overhead due to this method ranges from 1% to 10% for 16-b datapath circuits. On the other hand, hierarchical test patterns cannot provide good delay-fault coverage for faults in interconnection structure and registers. The reason is that some control sequences required for delay-fault detection cannot be provided by the controller. We propose two design-for-testability insertion methods to deal with this problem. Experimental results show that, on the average, at least 11% higher delay-fault coverage is achieved by these methods.