Logic testing and design for testability
Logic testing and design for testability
A design for testability technique for RTL circuits using control/data flow extraction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Orthogonal Scan: Low-Overhead Scan for Data Paths
Proceedings of the IEEE International Test Conference on Test and Design Validity
The Effect of Different Test Sets on Quality Level Prediction: When is 80% better than 90%?
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency
ATS '99 Proceedings of the 8th Asian Test Symposium
A Non-Scan DFT Method for Controllers to Achieve Complete Fault Efficiency
ATS '98 Proceedings of the 7th Asian Test Symposium
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
High-Level Synthesis for Orthogonal Scan
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Hierarchical test generation and design for testability methods for ASPPs and ASIPs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
High-level test synthesis for delay fault testability
Proceedings of the conference on Design, automation and test in Europe
A DFT method for time expansion model at register transfer level
Proceedings of the 44th annual Design Automation Conference
High-level test synthesis with hierarchical test generation for delay-fault testability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A study on insuring the full reliability of finite state machine
ICCSA'03 Proceedings of the 2003 international conference on Computational science and its applications: PartII
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