A non-scan DFT method at register-transfer level to achieve complete fault efficiency
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Non-Scan Design for Testability for Synchronous Sequential Circuits Based on Conflict Analysis
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution
IEEE Transactions on Computers
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As opposed to scan schemes, a non-scan DFT allows at-speed testing. This paper suggests three techniques on non-scan DFT of sequential circuits. The proposed techniques guarantee 100% fault efficiency by using combinational ATPG tool. In all techniques, an additional circuit called CRIS is proposed to reach unreachable states on the state register of a machine. The second and third techniques use an additional hardware called differentiating logic (DL), that uniquely identifies a state appearing in a state register. The design of DL is universal, i.e., not dependent on the circuit structure. Hardware overhead of DL and CRIS is lower than that of full scan. Test generation and application time are found to compare favorably with those of earlier designs.