A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability

Authors:
Satoshi Ohtake;Shintaro Nagai;Hiroki Wada;Hideo Fujiwara
Affiliations:
Graduate School of Information Science, Nara Institute of Science and Technology, 8916-5, Takayama, Ikoma, Nara 630-0101, Japan;Graduate School of Information Science, Nara Institute of Science and Technology, 8916-5, Takayama, Ikoma, Nara 630-0101, Japan;Graduate School of Information Science, Nara Institute of Science and Technology, 8916-5, Takayama, Ikoma, Nara 630-0101, Japan;Graduate School of Information Science, Nara Institute of Science and Technology, 8916-5, Takayama, Ikoma, Nara 630-0101, Japan
Venue:
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Year:
2001

Citing 5
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Abstract

This paper proposes a non-scan design-for-test-ability method for register-transfer level circuits where a circuit consists of a controller and a data path. It achieves complete fault efficiency with low hardware overhead and at-speed testing.