A design for testability technique for RTL circuits using control/data flow extraction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Functional design for testability of control-dominated architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hierarchical test generation and design for testability of ASPPs and ASIPs
DAC '97 Proceedings of the 34th annual Design Automation Conference
Design for Testability Techniques at the Behavioraland Register-Transfer Levels
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
High-Level Controllability and Observability Analysis for Test Synthesis
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Controller Resynthesis for Testability Enhancement of RTLController/Data Path Circuits
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Formal Value-Range and Variable Testability Techniquesfor High-Level Design-For-Testability
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
A non-scan DFT method at register-transfer level to achieve complete fault efficiency
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Behavioral-Level DFT via Formal Operator Testability Measures
Journal of Electronic Testing: Theory and Applications
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
ITC '97 Proceedings of the 1997 IEEE International Test Conference
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A DFT method for time expansion model at register transfer level
Proceedings of the 44th annual Design Automation Conference
RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences
Journal of Electronic Testing: Theory and Applications
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Most behavioral synthesis and design for testability techniques target subsequent gate-level sequential test generation, which is frequently incapable of handling complex controller/data path circuits with large data path bit-widths. Hierarchical testing attempts to counter the complexity of test generation by exploiting information from multiple levels of the design hierarchy. We present techniques that add minimal test hardware to the given register-transfer level (RTL) design obtained through behavioral synthesis in order to ensure that all the embedded modules in the circuit are hierarchically testable. An important by-product of our DFT procedure is a system-level test set that is guaranteed to deliver pre-computed module test sets to each module in the RTL circuit. This eliminates the need to apply gate-level sequential test generation to the controller/data path. We performed extensive experiments with several complex data path/controller circuits synthesized by two different high level synthesis systems which do not target testability.