Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Proofs: a fast, memory efficient sequential circuit fault simulator
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A design for testability technique for RTL circuits using control/data flow extraction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Blocking in a system on a chip
IEEE Spectrum
IEEE Spectrum
Hierarchical test generation and design for testability of ASPPs and ASIPs
DAC '97 Proceedings of the 34th annual Design Automation Conference
Code Generation for Embedded Processors
Code Generation for Embedded Processors
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Macro Testability: The Results of Production Device Applications
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Tutorial 3: Design and Test of Core-Based Systems
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Synthesis of application specific instruction sets
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has several advantages in terms of time-to-market and system cost, testing such core-based systems is difficult due to the problem of justifying test sequences at the inputs of a core embedded deep in the system, and propagating test responses from the core outputs. In this paper, we present a design for testability and symbolic test generation technique for testing such core-based systems on a chip.The proposed method consists of two parts: (i) core-level design for testability to make each core testable and transparent, the latter needed to propagate test data through the cores, and (ii) system-level design for testability and test generation to ensure the justification and propagation of the precomputed test sequences and test responses of the core. Since the hierarchical testability analys is technique used to tacklethe above problem is symbolic, the system test generation method is independent of the bit-width of the cores.The system-level test set is obtained as a by-product of the testability analysis and insertion method without further search Besides the proposed test method, the two methods that are currently used in the industry were also evaluated on twoexample systems: (i) FScan-BScan, where each core is full-scanned, and system test is performed using boundary scan, and (ii) FScan-TBus, where each core is full-scanned, andsystem test is performed using a test bus.The experiments show that the proposed scheme has significantly lower area overhead, delay overhead, and test application time compared to FScan-BScan and FScan-TBus, without any compromise in the system fault coverage.