DAC '98 Proceedings of the 35th annual Design Automation Conference
Efficient building block based RTL code generation from synchronous data flow graphs
Proceedings of the 37th Annual Design Automation Conference
Design methodologies for system level IP
Proceedings of the conference on Design, automation and test in Europe
Accumulator based deterministic BIST
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Formal engineering design synthesis
Mapping multirate dataflow to complex RT level hardware models
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
On core and more: a design perspective for systems-on-a-chip
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
1.2 Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
An IEEE 1149.1-Based Test Access Architecture for ICs with Embeddded Cores
ITC '97 Proceedings of the 1997 IEEE International Test Conference
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Test Requirements for Embedded Core-based Systems and IEEE P1500
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs
Proceedings of the 12th international symposium on System synthesis
International Journal of Computer Integrated Manufacturing - Global Competitive Manufacturing
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With more and larger functions being implemented on a single piece of silicon, true systems on a chip are being created. At the physical level, this integration derives from progress in process technology. But from the circuit designers' viewpoint, tools and methods are less help than they might be. In effect, to construct a system on a chip means more than the integration of millions of transistors. A set of complicated and rapidly evolving technologies and standards for telecommunications, multimedia, and PCs must be mastered, too. Also, the software content of most electronic systems has been growing for several years and now often accounts for a major part of the final product and hence of the design effort. Since a system on a chip is a system, a design methodology for generating such complex ICs will frequently have to address the software as well as hardware needs. Further more, as the size and complexity of chips has grown, so too has the task of verification. Verifying the design of a chip containing a million gates of logic presents a formidable challenge of its own. The complexity of large designs calls for a shift in the design paradigm to one based on reusable, high-level building blocks. Currently, most functional blocks are created by hand and are seldom used again. Reusable blocks, though, are not enough. To deliver on the promise of more productivity and less time to market, designers need reinforcements-a methodology and tools with which to integrate the blocks efficiently, plus standards that support the creation of reusable blocks, their exchange, and their integration