Blocking in a system on a chip
IEEE Spectrum
IEEE Spectrum
The Test Access Port and Boundary-Scan Architecture
The Test Access Port and Boundary-Scan Architecture
An IEEE 1149.1-Based Test Access Architecture for ICs with Embedded Cores
Proceedings of the IEEE International Test Conference
Testing TAPed cores and wrapped cores with the same test access mechanism
Proceedings of the conference on Design, automation and test in Europe
CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing
Journal of Electronic Testing: Theory and Applications
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Shared I/O-cell structures: a framework for extending the IEEE 1149.1 boundary-scan standard
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Delay Fault Testing of Designs with Embedded IP Cores
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Instruction-Driven Wake-Up Mechanisms for Snoopy TAP Controller
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
A Framework to evaluate Test Tradeoffs in Embedded Core Based Systems-Case Study on TT's TMS320C27xx
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Hierarchical Infrastructure for SoC Test Management
IEEE Design & Test
Searching for Global Test Costs Optimization in Core-Based Systems
Journal of Electronic Testing: Theory and Applications
Reusing an on-chip network for the test of core-based systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An efficient link controller for test access to IP core-based embedded system chips
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
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The rapid emergence of reusable core-based designs, in the last few years, poses new challenges to the IEEE test access standard 1149.1 [1,4]. Due to widespread industrial acceptance of 1149.1 standard, IC's are now expected to be 1149.1-compliant. At the same time, a typical IC, like the TMS470 microcontroller manufactured by TI, often contains multiple cores with built-in 1149.1- compliant Test Access Port (TAP), as well as significant amounts of non-core logic, which does not have any built-in test access mechanism. In this paper, we present a new TAP design that enables systematic integration of TAP'ed cores with non-TAP'ed logic, and makes the total IC 1149.1 compliant, at the same time. This TAP design, designated Hierarchical Test Access Port (HTAP), has exactly the same I/O pin specifications as an 1149.1-compliant TAP, and can either serve as an 1149.1-compliant TAP, or act as an arbitrator between existing TAPs in the embedded cores. Behavior of the HTAP -- whether to act as a TAP or as an arbitrator of TAPs -- is controlled via the TMS input pin.