Testing TAPed cores and wrapped cores with the same test access mechanism
Proceedings of the conference on Design, automation and test in Europe
Test Bus Sizing for System-on-a-Chip
IEEE Transactions on Computers
Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test
Journal of Electronic Testing: Theory and Applications
An IEEE 1149.1-Based Test Access Architecture for ICs with Embedded Cores
Proceedings of the IEEE International Test Conference
A hierarchical test control architecture for core based design
ATS '00 Proceedings of the 9th Asian Test Symposium
1.2 Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Wrapper Design for Embedded Core Test
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test scheduling for core-based systems using mixed-integer linear programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE standard 1500 compliance verification for embedded cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient SoC test technique by reusing on/off-chip bus bridge
IEEE Transactions on Circuits and Systems Part I: Regular Papers
ReBISR: a reconfigurable built-in self-repair scheme for random access memories in SOCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Integrating reusable cores from multiple sources is essential in system-on-a-chip design. The authors present a hierarchical methodology for testing these cores and the integrated system chip.