An efficient SoC test technique by reusing on/off-chip bus bridge

Authors:
Jaehoon Song;Hyunbean Yi;Juhee Han;Sungju Park
Affiliations:
Department of Computer Science and Engineering, Hanyang University, Kyeonggi-do, Korea;Dept. of Electrical and Computer Eng., Univ. of Massachusetts at Amherst, Amherst, MA;SAMSUNG Electronics, Yongin-si, Korea;Department of Computer Science and Engineering, Hanyang University, Kyeonggi-do, Korea
Venue:
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Year:
2009

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Abstract

Today's system-on-a-chip (SoC) is designed with reusable intellectual property cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficiently testable design technique is introduced for an SoC with an on/off-chip bus bridge for the on-chip advanced high-performance bus and off-chip peripheral-component-interconnect bus. The bridge is exploited by maximally reusing the bridge function to achieve efficient functional and structural testing. The testing time can be significantly reduced by increasing the number of test channels and shortening the test-control protocols. Experimental results show that area overhead and testing times are considerably reduced in both functional-and structural-test modes. The proposed technique can be extended to the other types of on/off-chip bus bridges.