Testing TAPed cores and wrapped cores with the same test access mechanism

CAS-BUS: a scalable and reconfigurable test access mechanisms for systems on a chip

DATE '00 Proceedings of the conference on Design, automation and test in Europe

An IEEE 1149.1-Based Test Access Architecture for ICs with Embedded Cores

Proceedings of the IEEE International Test Conference

A structured test re-use methodology for core-based system chips

ITC '98 Proceedings of the 1998 IEEE International Test Conference

A structured and scalable mechanism for test access to embedded reusable cores

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Solving the I/O Bandwidth Problem in System on a Chip Testing

SBCCI '00 Proceedings of the 13th symposium on Integrated circuits and systems design

1.2 Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

Towards a Standard for Embedded Core Test: An Example

ITC '99 Proceedings of the 1999 IEEE International Test Conference

Addressable Test Ports An Approach to Testing Embedded Cores

ITC '99 Proceedings of the 1999 IEEE International Test Conference