Solving the I/O Bandwidth Problem in System on a Chip Testing

Authors:
W. Maroufi;M. Benabdenbi;M. Marzouki
Affiliations:
-;-;-
Venue:
SBCCI '00 Proceedings of the 13th symposium on Integrated circuits and systems design
Year:
2000

Citing 0
Cited 2

Testing TAPed cores and wrapped cores with the same test access mechanism

Proceedings of the conference on Design, automation and test in Europe
CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing

Journal of Electronic Testing: Theory and Applications

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Abstract

The first part of this paper describes the control of CAS-BUS, a P1500 compatible Test Access Mechanism (TAM). Boundary scan features are used to allow controlling of the TAM and the P1500 wrappers. The final architecture characteristics are its flexibility, scalability and reconfigurability. It also allows trade-off to optimize test time and area overhead. The second part deals with a test pin expansion method in order to solve the bandwidth problem. The solution we propose is based on a new compression/decompression mechanism which avoid TAM performances degradation.