Digital receiver design using VHDL generation from data flow graphs
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Blocking in a system on a chip
IEEE Spectrum
Digital Communication Receivers: Synchronization, Channel Estimation, and Signal Processing
Digital Communication Receivers: Synchronization, Channel Estimation, and Signal Processing
Mapping multirate dataflow to complex RT level hardware models
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Efficient hardware controller synthesis for synchronous dataflow graph in system level design
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Hardware synthesis from SPDF representation for multimedia applications
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Efficient hardware controller synthesis for synchronous dataflow graph in system level design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis
Journal of Signal Processing Systems
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Correct and non-defensive glue design using abstract models
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Mapping Parameterized Cyclo-static Dataflow Graphs onto Configurable Hardware
Journal of Signal Processing Systems
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In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is composed of high level building blocks of which some are reused from previous designs while others might have been created by behavioral synthesis. In data flow oriented designs, these blocks usually have complex non-matching interface properties, making it necessary to generate additional interfacing and controlling hardware to integrate them into an operable system.In this paper, an RTL-HDL code generation from a synchronous data flow representations is introduced, that efficiently automates the generation of the required additional hardware. While existing code generation approaches provide strong limitations concerning the building block interfacing properties, our method enables the integration of components that access their ports periodically with arbitrary patterns. In order to reduce interface register cost, a minimum-area retiming approach is taken to determine optimum building block activation times, which is known to have polynomial time complexity. The code generation methodology is compared to an existing approach using a simple case study.