Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
A case against event-driven simulation for digital system design
ANSS '91 Proceedings of the 24th annual symposium on Simulation
Consistency in Dataflow Graphs
IEEE Transactions on Parallel and Distributed Systems
System level fixed-point design based on an interpolative approach
DAC '97 Proceedings of the 34th annual Design Automation Conference
Efficient building block based RTL code generation from synchronous data flow graphs
Proceedings of the 37th Annual Design Automation Conference
FRIDGE: a fixed-point design and simulation environment
Proceedings of the conference on Design, automation and test in Europe
A dataflow specification for system level synthesis of 3D graphics applications
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Efficient hardware controller synthesis for synchronous dataflow graph in system level design
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Hardware synthesis from SPDF representation for multimedia applications
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Efficient hardware controller synthesis for synchronous dataflow graph in system level design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On core and more: a design perspective for systems-on-a-chip
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
PCC: a modeling technique for mixed control/data flow systems
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs
Proceedings of the 12th international symposium on System synthesis
Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis
Journal of Signal Processing Systems
Correct and non-defensive glue design using abstract models
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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