Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
Cathedral-III: Architecture-driven high-level synthesis for high throughput DSP applications
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Increasing design quality and engineering productivity through design reuse
DAC '93 Proceedings of the 30th international Design Automation Conference
Hardware/software co-simulation
DAC '94 Proceedings of the 31st annual Design Automation Conference
High-speed VLSI architectures for soft-output Viterbi decoding
Journal of VLSI Signal Processing Systems - Special issue on application specific array processors (ASAP-92)
Digital receiver design using VHDL generation from data flow graphs
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Blocking in a system on a chip
IEEE Spectrum
PCC: a modeling technique for mixed control/data flow systems
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Unified Specification of Control and Data Flow
ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97) -Volume 1 - Volume 1
Soft-cores generation by instruction set analysis
Proceedings of the 14th international symposium on Systems synthesis
Design methodology for digital signal processing
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
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In this survey, key drivers in design methodology are provided that enable successful design of systems-on-a-chip for the highly competitive telecommunications market. Main components of a design environment are described that fulfill the requirements of today's system design: efficient verification by means of fast simulation, integration of intellectual property, support of HW/SW co-design by means of a generic machine description language, generation of dedicated hardware blocks for high speed applications, and the link from system level performance evaluation to implementations in hardware and software.