Architectures and design techniques for real-time image processing ics (recognition)
Architectures and design techniques for real-time image processing ics (recognition)
Time constrained allocation and assignment techniques for high throughput signal processing
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Design of heterogeneous ICs for mobile and personal communication systems
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Structured design methodology for high-level design
DAC '94 Proceedings of the 31st annual Design Automation Conference
Synthesis of signal processing structured datapaths for FPGAs supporting RAMs and busses
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Scheduling using behavioral templates
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Synthesis of pipelined DSP accelerators with dynamic scheduling
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Custom-fit processors: letting applications define architectures
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
High throughput pipelined data path synthesis by conserving the regularity of nested loops
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Instruction set mapping for performance optimization
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Quadratic zero-one programming based synthesis of application specific data paths
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Journal of VLSI Signal Processing Systems - Special issue on the 1997 IEEE workshop on signal processing systems (SiPS): design and implementation
Watermarking while preserving the critical path
Proceedings of the 37th Annual Design Automation Conference
Analysis of high-level address code transformations for programmable processors
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Architectural simulation in the context of behavioral synthesis
Proceedings of the conference on Design, automation and test in Europe
ShiftQ: a bufferred interconnect for custom loop accelerators
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
CoWare---a design environment for heterogeneous hardware/software systems
Readings in hardware/software co-design
Instruction generation and regularity extraction for reconfigurable processors
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Instruction generation for hybrid reconfigurable systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On core and more: a design perspective for systems-on-a-chip
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Architectural Exploration and Optimization for Counter Based Hardware Address Generation
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Designing Systems On Silicon: A Digital Spread Spectrum Pager
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Formal Techniques for Hardware Allocation
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
ADOPT: Efficient Hardware Address Generation in Distributed Memory Architectures
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
A formal method for hardware IP design and integration under I/O and timing constraints
ACM Transactions on Embedded Computing Systems (TECS)
Streamroller:: automatic synthesis of prescribed throughput accelerator pipelines
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Increasing hardware efficiency with multifunction loop accelerators
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
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