Architectural Exploration and Optimization for Counter Based Hardware Address Generation

Authors:
M. Miranda;M. Kaspar;F. Catthoor;H. de Man
Affiliations:
IMEC, Kapeldreef 75, B-3001 Leuven, Belgium;IMEC, Kapeldreef 75, B-3001 Leuven, Belgium;Professor at the Katholieke Universiteit Leuven;Professor at the Katholieke Universiteit Leuven
Venue:
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Year:
1997

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Abstract

A set of automated system level techniques is presented for architectural exploration and optimization of counter based address generation units in real time signal processing systems. The goal is to explore different architectural alternatives available when mapping array references in order to select the most promising ones in area cost. The techniques are demonstrated on realistic test-vehicles, showing that architectural decision at early stages of the design process, can have a very large impact on the resulting area figure.