ADOPT: Efficient Hardware Address Generation in Distributed Memory Architectures

Authors:
Miguel Miranda;Francky Catthoor;Martin Janssen; Hugo de Man
Affiliations:
IMEC Lab. Kapeldreef 75, 3001 Leuven, Belgium.;Professor at the Katholieke Universiteit Leuven;IMEC Lab. Kapeldreef 75, 3001 Leuven, Belgium.;Professor at the Katholieke Universiteit Leuven
Venue:
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Year:
1996

Citing 8
Cited 9

Compilers: principles, techniques, and tools

Compilers: principles, techniques, and tools
Time constrained allocation and assignment techniques for high throughput signal processing

DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Cathedral-III: Architecture-driven high-level synthesis for high throughput DSP applications

DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Beyond induction variables: detecting and classifying sequences using a demand-driven SSA form

ACM Transactions on Programming Languages and Systems (TOPLAS)
Address generation for memories containing multiple arrays

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A specification invariant technique for operation cost minimisation in flow-graphs

ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Address Generation for array access based on modulus m counters

EURO-DAC '91 Proceedings of the conference on European design automation
PHIDEO: a silicon compiler for high speed algorithms

EURO-DAC '91 Proceedings of the conference on European design automation

Efficient system exploration and synthesis of applications with dynamic data storage and intensive data transfer

DAC '98 Proceedings of the 35th annual Design Automation Conference
Matisse: A System-on-Chip Design Methodology Emphasizing Dynamic Memory Management

Journal of VLSI Signal Processing Systems - Special issue on system level design
Analysis of high-level address code transformations for programmable processors

DATE '00 Proceedings of the conference on Design, automation and test in Europe
Loop fusion for memory space optimization

Proceedings of the 14th international symposium on Systems synthesis
Architectural Exploration and Optimization for Counter Based Hardware Address Generation

EDTC '97 Proceedings of the 1997 European conference on Design and Test
Address Code and Arithmetic Optimizations for Embedded Systems

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Algorithmic-level Specification and Characterization of Embedded Multimedia Applications with Design Trotter

Journal of VLSI Signal Processing Systems
Address Generation Optimization for Embedded High-Performance Processors: A Survey

Journal of Signal Processing Systems
Synthesis of multi-dimensional high-speed FIFOs for out-of-order communication

ARCS'08 Proceedings of the 21st international conference on Architecture of computing systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

An address generation and optimization environment (ADOPT) for distributed memory architectures, is presented. ADOPT is oriented to minimize the area overhead introduced by the use of large numbers of customized address calculation units, needed to cope with the increasing bandwidth requirements of memory intensive real-time signal processing applications. Different high-level optimizing architectural alternatives are explored, such as algebraic optimizations and efficient data-path clustering and assignment, to minimize the space/time-multiplexed address unit cost. Furthermore, in order to significantly reduced the routing complexity, typically present in partitioned architectures, a methodology for the synthesis of a distributed architecture for hierarchical local controllers for address generation, is also proposed. The techniques presented are demonstrated on a realistic test-vehicle, showing significant savings on the overall addressing cost.