Definition and solution of the memory packing problem for field-programmable systems
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Codesign of embedded systems: status and trends
Readings in hardware/software co-design
Codesign of Embedded Systems: Status and Trends
IEEE Design & Test
Generating Addresses for Multi-dimensional Array Access in FPGA On-chip Memory
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
ADOPT: Efficient Hardware Address Generation in Distributed Memory Architectures
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Address Generation Optimization for Embedded High-Performance Processors: A Survey
Journal of Signal Processing Systems
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This paper presents techniques for generating addresses for memories containing multiple arrays. Because these techniques rely on the inversion or rearrangement of address bits, they are faster and require less hardware to compute than offset addition. Use of these techniques can decrease effective access time to arrays and reduce address generation hardware. The primary drawback is that extra memory space is occasionally required by these techniques, but this extra memory space is on average only 4% and no worse than 25.2% of the utilized memory space. This amount of wasted address space is less than the amount required by similar techniques.