Instruction Set Design and Optimizations for Address Computation in DSP Architectures

  • Authors:

  • Guido Araujo;Ashok Sudarsanam;Sharad Malik

  • Affiliations:

  • Department of Electrical Engineering, Princeton University, Princeton, New Jersey;Department of Electrical Engineering, Princeton University, Princeton, New Jersey;Department of Electrical Engineering, Princeton University, Princeton, New Jersey

  • Venue:
  • ISSS '96 Proceedings of the 9th international symposium on System synthesis
  • Year:
  • 1996

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Abstract

In this paper we investigate the problem of code generation for address computation for DSP processors. This work is divided into four parts. First, we propose a branch instruction design which can guarantee minimum overhead for programs that make use of implicit indirect addressing. Second, we give a formulation and propose a solution for the problem of allocating address registers (ARs) for array accesses within loop constructs. Third, we describe retargetable approaches for auto-increment (decrement) optimizations of pointer variables, and loop induction variables. Finally, we use a graph coloring technique to allocate physical ARs to the virtual ARs used in the previous phases. The results show that the combination of the above techniques considerably improves the final code quality for benchmark DSP programs.