Register-constrained address computation in DSP programs

Authors:
A. Basu;R. Leupers;P. Marwedel
Affiliations:
University of Dortm und, Department of Computer Science 12, 44221 Dortm und, Germany;University of Dortm und, Department of Computer Science 12, 44221 Dortm und, Germany;University of Dortm und, Department of Computer Science 12, 44221 Dortm und, Germany
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
1998

Citing 4
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Abstract

This paper describes a new code optimization technique for digital signal processors (DSPs). One important characteristic of DSP algorithms are iterative accesses to data array elements within loops. DSPs support efficient address computations for such array accesses by means of dedicated address generation units (AGUs). We present a heuristic technique which, given an AGU with a fixed number of address registers, minimizes the number of instructions needed for array address computations in a program loop.