Bulldog: a compiler for VLSI architectures
Bulldog: a compiler for VLSI architectures
Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Code optimization techniques for embedded DSP microprocessors
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
The Art of Programming Embedded Systems
The Art of Programming Embedded Systems
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
Code density optimization for embedded DSP processors using data compression techniques
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
The SUIF Compiler System: a Parallelizing and Optimizing Research Compiler
The SUIF Compiler System: a Parallelizing and Optimizing Research Compiler
A compiler for application-specific signal processors
A compiler for application-specific signal processors
Code optimization techniques for embedded DSP microprocessors
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Optimal code generation for embedded memory non-homogeneous register architectures
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Memory bank and register allocation in software synthesis for ASIPs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Optimized code generation of multiplication-free linear transforms
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Optimizing systems for effective block-processing: the k-delay problem
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Algorithms for address assignment in DSP code generation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
An efficient model for DSP code generation: performance, code size, estimated energy
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Code generation for core processors
DAC '97 Proceedings of the 34th annual Design Automation Conference
DSP address optimization using a minimum cost circulation technique
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Memory data organization for improved cache performance in embedded processor applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A uniform optimization technique for offset assignment problems
Proceedings of the 11th international symposium on System synthesis
Storage assignment optimizations to generate compact and efficient code on embedded DSPs
Proceedings of the ACM SIGPLAN 1999 conference on Programming language design and implementation
Simultaneous reference allocation in code generation for dual data memory bank ASIPs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Function inlining under code size constraints for embedded processors
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Optimizing computations for effective block-processing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Register-constrained address computation in DSP programs
Proceedings of the conference on Design, automation and test in Europe
Register allocation for common subexpressions in DSP data paths
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Optimized address assignment for DSPs with SIMD memory accesses
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Scheduling-based code size reduction in processors with indirect addressing mode
Proceedings of the ninth international symposium on Hardware/software codesign
Address code generation for digital signal processors
Proceedings of the 38th annual Design Automation Conference
C Compiler Design for an Industrial Network Processor
OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
Code generation for embedded processors
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Address assignment combined with scheduling in DSP code generation
Proceedings of the 39th annual Design Automation Conference
Global array reference allocation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Embedded software in real-time signal processing systems: design technologies
Readings in hardware/software co-design
Compiler Design Issues for Embedded Processors
IEEE Design & Test
Improving Offset Assignment on Embedded Processors Using Transformations
HiPC '00 Proceedings of the 7th International Conference on High Performance Computing
Improving Offset Assignment for Embedded Processors
LCPC '00 Proceedings of the 13th International Workshop on Languages and Compilers for Parallel Computing-Revised Papers
Array Reference Allocation Using SSA-Form and Live Range Growth
LCTES '00 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
A network flow approach to memory bandwidth utilization in embedded DSP core processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Storage assignment optimizations through variable coalescence for embedded processors
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
Memory Organization for Improved Data Cache Performance in Embedded Processors
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Simple offset assignment in presence of subword data
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Specific optimization features in a C compiler for DSPs
Programming and Computing Software
Reducing code size through address register assignment
ACM Transactions on Embedded Computing Systems (TECS)
Allocating architected registers through differential encoding
ACM Transactions on Programming Languages and Systems (TOPLAS)
UCC: update-conscious compilation for energy efficiency in wireless sensor networks
Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation
Memory Offset Assignment for DSPs
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
Function Inlining in Embedded Systems with Code Size Limitation
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
Towards update-conscious compilation for energy-efficient code dissemination in WSNs
ACM Transactions on Architecture and Code Optimization (TACO)
An optimization framework for embedded processors with auto-addressing mode
ACM Transactions on Programming Languages and Systems (TOPLAS)
Usability evaluation of Korean e-government portal
UAHCI'07 Proceedings of the 4th international conference on Universal access in human-computer interaction: applications and services
Offset assignment showdown: evaluation of DSP address code optimization algorithms
CC'03 Proceedings of the 12th international conference on Compiler construction
Exploiting parallelism in memory operations for code optimization
LCPC'04 Proceedings of the 17th international conference on Languages and Compilers for High Performance Computing
Storage Optimization through Offset Assignment with Variable Coalescing
ACM Transactions on Embedded Computing Systems (TECS)
An ILP solution to address code generation for embedded applications on digital signal processors
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Minimizing address arithmetic instructions in embedded applications on DSPs
Computers and Electrical Engineering
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DSP architectures typically provide indirect addressing modes with auto-increment and decrement. In addition, indexing mode is not available, and there are usually few, if any, general-purpose registers. Hence, it is necessary to use address registers and perform address arithmetic to access automatic variables. Subsuming the address arithmetic into auto-increment and auto-decrement modes improves the size of the generated code.In this paper we present a formulation of the problem of optimal storage assignment such that explicit instructions for address arithmetic are minimized. We prove that for the case of a single address register the decision problem is NP-complete. We then generalize the problem to multiple address registers. For both cases heuristic algorithms are given. Our experimental results indicate an improvement of 3.