Optimized address assignment for DSPs with SIMD memory accesses

Authors:
Markus Lorenz;David Koffmann;Steven Bashford;Rainer Leupers;Peter Marwedel
Affiliations:
Dept. of Computer Science 12, University of Dortmund, Germany;Dept. of Computer Science 12, University of Dortmund, Germany;Dept. of Computer Science 12, University of Dortmund, Germany;Dept. of Computer Science 12, University of Dortmund, Germany;Dept. of Computer Science 12, University of Dortmund, Germany
Venue:
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Year:
2001

Citing 9
Cited 7

Adaptation in natural and artificial systems

Adaptation in natural and artificial systems
Storage assignment to decrease code size

PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Memory bank and register allocation in software synthesis for ASIPs

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Evolutionary algorithms in theory and practice: evolution strategies, evolutionary programming, genetic algorithms

Evolutionary algorithms in theory and practice: evolution strategies, evolutionary programming, genetic algorithms
Exploiting dual data-memory banks in digital signal processors

Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Algorithms for address assignment in DSP code generation

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A uniform optimization technique for offset assignment problems

Proceedings of the 11th international symposium on System synthesis
Computers and Intractability: A Guide to the Theory of NP-Completeness

Computers and Intractability: A Guide to the Theory of NP-Completeness
MicroUnity's MediaProcessor Architecture

IEEE Micro

Energy aware compilation for DSPs with SIMD instructions

Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Embedded intelligent SRAM

Proceedings of the 40th annual Design Automation Conference
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks

Proceedings of the conference on Design, automation and test in Europe - Volume 1
Background Data Organisation for the Low-Power Implementation in Real-Time of a Digital Audio Broadcast Receiver on a SIMD Processor

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Energy-aware variable partitioning and instruction scheduling for multibank memory architectures

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Loop scheduling and bank type assignment for heterogeneous multi-bank memory

Journal of Parallel and Distributed Computing
Variable assignment and instruction scheduling for processor with multi-module memory

Microprocessors & Microsystems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper deals with address assignment in code generation for digital signal processors (DSPs) with SIMD (single instruction multiple data) memory accesses. In these processors data are organized in groups (or partitions), whose elements share one common memory address. In order to optimize program performance for processors with such memory architectures it is important to have a suitable memory layout of the variables. We propose a two-step address assignment technique for scalar variables using a genetic algorithm based partitioning method and a graph based heuristic which makes use of available DSP address generation hardware. We show that our address assignment techniques lead to a significant code quality improvement compared to heuristics.