Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Software pipelining: an effective scheduling technique for VLIW machines
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
The multiflow trace scheduling compiler
The Journal of Supercomputing - Special issue on instruction-level parallelism
Software synthesis for DSP using Ptolemy
Journal of VLSI Signal Processing Systems - Special issue on design environments for DSP
IEEE Spectrum - Special issue: technology 1995
Memory bank and register allocation in software synthesis for ASIPs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Local Microcode Compaction Techniques
ACM Computing Surveys (CSUR)
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
The visual instruction set (VIS) in UltraSPARC
COMPCON '95 Proceedings of the 40th IEEE Computer Society International Conference
Very Long Instruction Word architectures and the ELI-512
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Evaluating MMX technology using DSP and multimedia applications
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Simultaneous reference allocation in code generation for dual data memory bank ASIPs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Memory bank customization and assignment in behavioral synthesis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimized address assignment for DSPs with SIMD memory accesses
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Dynamic Programming Approach to Optimal Integrated Code Generation
OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
Code generation for embedded processors
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Compiler Support for Scalable and Efficient Memory Systems
IEEE Transactions on Computers
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Readings in hardware/software co-design
Evaluation of Neural and Genetic Algorithms for Synthesizing Parallel Storage Schemes
International Journal of Parallel Programming
Memory Architectures for Embedded Systems-On-Chip
HiPC '02 Proceedings of the 9th International Conference on High Performance Computing
Variable Partitioning and Scheduling of Multiple Memory Architectures for DSP
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
A Framework for Parallelizing Load/Stores on Embedded Processors
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques
PROPAN: A Retargetable System for Postpass Optimisations and Analyses
LCTES '00 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
Optimal Code and Data Layout in Embedded Systems
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Exploiting bank locality in multi-bank memories
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Fast memory bank assignment for fixed-point digital signal processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Impact of Data Transformations on Memory Bank Locality
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks
Proceedings of the conference on Design, automation and test in Europe - Volume 1
EMBARC: an efficient memory bank assignment algorithm for retargetable compilers
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Array organization in parallel memories
International Journal of Parallel Programming
Nonuniform Banking for Reducing Memory Energy Consumption
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Integer linear programming based energy optimization for banked DRAMs
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Energy-aware variable partitioning and instruction scheduling for multibank memory architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Exploiting Inter-Processor Data Sharing for Improving Behavior of Multi-Processor SoCs
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Retargetable code generation for application-specific processors
Future Generation Computer Systems - Special issue: Parallel computing technologies
Specific optimization features in a C compiler for DSPs
Programming and Computing Software
Data Replication in Banked DRAMs for Reducing Energy Consumption
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Parallelizing load/stores on dual-bank memory embedded processors
ACM Transactions on Embedded Computing Systems (TECS)
Comparing a genetic algorithm penalty function and repair heuristic in the DSP application domain
AIA'06 Proceedings of the 24th IASTED international conference on Artificial intelligence and applications
Minimizing bank selection instructions for partitioned memory architecture
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Journal of Systems and Software
Cache miss clustering for banked memory systems
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Fast, accurate design space exploration of embedded systems memory configurations
Proceedings of the 2007 ACM symposium on Applied computing
An Efficient Code Generation Algorithm for Non-orthogonal DSP Architecture
Journal of VLSI Signal Processing Systems
Integration, the VLSI Journal
Minimal placement of bank selection instructions for partitioned memory architectures
ACM Transactions on Embedded Computing Systems (TECS)
Fast source-level data assignment to dual memory banks
SCOPES '08 Proceedings of the 11th international workshop on Software & compilers for embedded systems
ILP-Based energy minimization techniques for banked memories
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Loop scheduling and bank type assignment for heterogeneous multi-bank memory
Journal of Parallel and Distributed Computing
Retargetable code generation for application-specific processors
Future Generation Computer Systems - Special issue: Parallel computing technologies
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Variable assignment and instruction scheduling for processor with multi-module memory
Microprocessors & Microsystems
Run-Time memory optimization for DDMB architecture through a CCB algorithm
EUC'06 Proceedings of the 2006 international conference on Emerging Directions in Embedded and Ubiquitous Computing
A novel genetic algorithm for variable partition of dual memory bank DSPs
ICNC'05 Proceedings of the First international conference on Advances in Natural Computation - Volume Part III
On-chip memory architecture exploration framework for DSP processor-based embedded system on chip
ACM Transactions on Embedded Computing Systems (TECS)
Journal of Combinatorial Optimization
Adaptive Source-Level Data Assignment to Dual Memory Banks
ACM Transactions on Embedded Computing Systems (TECS)
ACM Transactions on Embedded Computing Systems (TECS)
Minimizing code size via page selection optimization on partitioned memory architectures
Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
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Over the past decade, digital signal processors (DSPs) have emerged as the processors of choice for implementing embedded applications in high-volume consumer products. Through their use of specialized hardware features and small chip areas, DSPs provide the high performance necessary for embedded applications at the low costs demanded by the high-volume consumer market. One feature commonly found in DSPs is the use of dual data-memory banks to double the memory system's bandwidth. When coupled with high-order data interleaving, dual memory banks provide the same bandwidth as more costly memory organizations such as a dual-ported memory. However, making effective use of dual memory banks remains difficult, especially for high-level language (HLL) DSP compilers.In this paper, we describe two algorithms --- compaction-based (CB) data partitioning and partial data duplication --- that we developed as part of our research into the effective exploitation of dual data-memory banks in HLL DSP compilers. We show that CB partitioning is an effective technique for exploiting dual data-memory banks, and that partial data duplication can augment CB partitioning in improving execution performance. Our results show that CB partitioning improves the performance of our kernel benchmarks by 13%-40% and the performance of our application benchmarks by 3%-15%. For one of the application benchmarks, partial data duplication boosts performance from 3% to 34%.