Integer and combinatorial optimization
Integer and combinatorial optimization
Exploiting dual data-memory banks in digital signal processors
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Memory bank customization and assignment in behavioral synthesis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Energy-oriented compiler optimizations for partitioned memory architectures
CASES '00 Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Memory controller policies for DRAM power management
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Improving memory energy using access pattern classification
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Influence of Loop Optimizations on Energy Consumption of Multi-bank Memory Systems
CC '02 Proceedings of the 11th International Conference on Compiler Construction
DRAM Energy Management Using Sof ware and Hardware Directed Power Mode Control
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Integer linear programming based energy optimization for banked DRAMs
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Modeling of DRAM power control policies using deterministic and stochastic Petri nets
PACS'02 Proceedings of the 2nd international conference on Power-aware computer systems
ZettaRAM: A Power-Scalable DRAM Alternative through Charge-Voltage Decoupling
IEEE Transactions on Computers
PPT: joint performance/power/thermal management of DRAM memory for multi-core systems
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
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Due to continuously increasing importance of memory systems, there have been a plethora of studies in the last decade to improve their performance and power consumption behavior. Banked memories have been the focus of several recent efforts that attempt to reduce power consumption and have been studied from both the hardware and software angles. One of the common assumptions made implicitly by all these prior efforts is that each data block has only a single copy in the banked memory system. This assumption, while preferable from the viewpoint of reducing the total memory footprint of program data, may cause unnecessary power consumption in the context of banked memories. Motivated by this observation, this paper proposes and evaluates a novel power management scheme for balanced memories based on data replication. The idea behind our approach is to use replication to prevent re-activating an otherwise idle memory bank. To achieve this, we implemented both a heuristic and an ILP based solution to the data placement and replication problem in a banked architecture.