Exploiting dual data-memory banks in digital signal processors
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Variable Partitioning and Scheduling of Multiple Memory Architectures for DSP
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
A Framework for Parallelizing Load/Stores on Embedded Processors
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques
Influence of Loop Optimizations on Energy Consumption of Multi-bank Memory Systems
CC '02 Proceedings of the 11th International Conference on Compiler Construction
Fast memory bank assignment for fixed-point digital signal processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Energy-aware variable partitioning and instruction scheduling for multibank memory architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Minimizing bank selection instructions for partitioned memory architecture
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Minimal placement of bank selection instructions for partitioned memory architectures
ACM Transactions on Embedded Computing Systems (TECS)
Optimizing Bank Selection Instructions by Using Shared Memory
ICESS '08 Proceedings of the 2008 International Conference on Embedded Software and Systems
Register loading via linear programming
WADS'11 Proceedings of the 12th international conference on Algorithms and data structures
ACM Transactions on Embedded Computing Systems (TECS)
Optimal placement of bank selection instructions in polynomial time
Proceedings of the 16th International Workshop on Software and Compilers for Embedded Systems
Minimizing code size via page selection optimization on partitioned memory architectures
Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
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A large number of embedded systems include 8-bit microcontrollers for their energy efficiency and low cost. Multi-bank memory architecture is commonly applied in 8-bit microcontrollers to increase the size of memory without extending address buses. To switch among different memory banks, a special instruction, Bank Selection, is used. How to minimize the number of bank selection instructions inserted is important to reduce code size for embedded systems. In this paper, we consider how to insert the minimum number of bank selection instructions in a program to achieve feasibility. A program can be represented by a control flow graph (CFG). We prove that it is NP-Hard to insert the minimum number of bank selection instructions if all the variables are pre-assigned to memory banks. Therefore, we introduce a 2-approximation algorithm using a rounding method. When the CFG is a tree or the out-degree of each node in the CFG is at most two, we show that we can insert the bank selection instructions optimally in polynomial time. We then consider the case when there are some nodes that do not access any memory bank and design a dynamic programming method to compute the optimal insertion strategy when the CFG is a tree. Experimental result shows the proposed techniques can reduce bank selection instructions significantly on partitioned memory architecture.