Register connection: a new approach to adding registers into instruction set architectures
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
A Linear-Time Algorithm for Finding Tree-Decompositions of Small Treewidth
SIAM Journal on Computing
All structured programs have small tree width and good register allocation
Information and Computation
Linear-time register allocation for a fixed number of registers
Proceedings of the ninth annual ACM-SIAM symposium on Discrete algorithms
The Treewidth of Java Programs
ALENEX '02 Revised Papers from the 4th International Workshop on Algorithm Engineering and Experiments
Minimizing bank selection instructions for partitioned memory architecture
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Minimal placement of bank selection instructions for partitioned memory architectures
ACM Transactions on Embedded Computing Systems (TECS)
Optimizing Bank Selection Instructions by Using Shared Memory
ICESS '08 Proceedings of the 2008 International Conference on Embedded Software and Systems
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Optimal register allocation in polynomial time
CC'13 Proceedings of the 22nd international conference on Compiler Construction
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We present the first approach to Optimal Placement of Bank Selection Instructions in Polynomial Time; previous approaches were not optimal or did not provably run in polynomial time. Our approach requires the input program to be structured, which is automatically true for many programming languages and for others, such as C, is equivalent to a bound on the number of goto labels per function. When not restricted to structured programs, the problem is NP-hard. A prototype implementation in a mainstream compiler for embedded systems shows the practical feasibility of our approach. Our approach and implementation are easy to retarget for different optimization goals and architectures.