Improving locality and parallelism in nested loops
Improving locality and parallelism in nested loops
A singular loop transformation framework based on non-singular matrices
International Journal of Parallel Programming
Exploiting dual data-memory banks in digital signal processors
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Memory-CPU size optimization for embedded system designs
DAC '97 Proceedings of the 34th annual Design Automation Conference
Advanced compiler design and implementation
Advanced compiler design and implementation
Improving Cache Locality by a Combination of Loop and Data Transformations
IEEE Transactions on Computers - Special issue on cache memory and related problems
An efficient architecture model for systematic design of application-specific multiprocessor SoC
Proceedings of the conference on Design, automation and test in Europe
Dynamic management of scratch-pad memory space
Proceedings of the 38th annual Design Automation Conference
An optimal memory allocation for application-specific multiprocessor system-on-chip
Proceedings of the 14th international symposium on Systems synthesis
Optimizing compilers for modern architectures: a dependence-based approach
Optimizing compilers for modern architectures: a dependence-based approach
Exploiting shared scratch pad memory space in embedded multiprocessor systems
Proceedings of the 39th annual Design Automation Conference
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
PROPHID: a heterogeneous multi-processor architecture for multimedia
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Assigning Program and Data Objects to Scratchpad for Energy Reduction
Proceedings of the conference on Design, automation and test in Europe
Local memory exploration and optimization in embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies
Proceedings of the 43rd annual Design Automation Conference
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Software-managed memories are important in real-time embedded environments where execution time predictability is an important requirement. With the proliferation of embedded multi-processor systems, software support for their memories is becoming an attractive research area in real-time embedded computing. One of the critical problems in embedded real-time multi-processor SoCs (System-on-a-Chip) is to reduce the number of off-chip references. This is because frequent off-chip references can be very costly from both performance and power perspectives. In this paper, we propose a novel compiler-driven strategy for reducing the number of off-chip references, which is based on co-operation between the processors in the multi-processor architecture. Specifically, in the proposed strategy, the processors cache data in their local memories, under compiler control, on behalf of each other if doing so reduces the number of off-chip references.