Dynamic management of scratch-pad memory space

  • Authors:

  • M. Kandemir;J. Ramanujam;J. Irwin;N. Vijaykrishnan;I. Kadayif;A. Parikh

  • Affiliations:

  • Microsystems Design Lab, The Pennsylvania State University, University Park, PA;Department of ECE, Louisiana State University, Baton Rouge, LA;Microsystems Design Lab, The Pennsylvania State University, University Park, PA;Microsystems Design Lab, The Pennsylvania State University, University Park, PA;Microsystems Design Lab, The Pennsylvania State University, University Park, PA;Microsystems Design Lab, The Pennsylvania State University, University Park, PA

  • Venue:
  • Proceedings of the 38th annual Design Automation Conference
  • Year:
  • 2001

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Abstract

Optimizations aimed at improving the efficiency of on-chip memories are extremely important. We propose a compiler-controlled dynamic on-chip scratch-pad memory (SPM) management framework that uses both loop and data transformations. Experimental results obtained using a generic cost model indicate significant reductions in data transfer activity between SPM and off-chip memory.