A novel instruction scratchpad memory optimization method based on concomitance metric

  • Authors:

  • Andhi Janapsatya;Aleksandar Ignjatović;Sri Parameswaran

  • Affiliations:

  • The University of New South Wales, Sydney, Australia;The University of New South Wales, Sydney, Australia;The University of New South Wales, Sydney, Australia

  • Venue:
  • ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
  • Year:
  • 2006

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Abstract

Scratchpad memory has been introduced as a replacement for cache memory as it improves the performance of certain embedded systems. Additionally, it has also been demonstrated that scratchpad memory can significantly reduce the energy consumption of the memory hierarchy of embedded systems. This is significant, as the memory hierarchy consumes a substantial proportion of the total energy of an embedded system. This paper deals with optimization of the instruction memory scratchpad based on a novel methodology that uses a metric which we call the concomitance. This metric is used to find basic blocks which are executed frequently and in close proximity in time. Once such blocks are found, they are copied into the scratchpad memory at appropriate times; this is achieved using a special instruction inserted into the code at appropriate places. For a set of benchmarks taken from Mediabench, our scratchpad system consumed just 59% (avg) of the energy of the cache system, and 73% (avg) of the energy of the state of the art scratchpad system, while improving the overall performance. Compared to the state of the art method, the number of instructions copied into the scratchpad memory from the main memory is reduced by 88%.