Timing Anomalies in Dynamically Scheduled Microprocessors
RTSS '99 Proceedings of the 20th IEEE Real-Time Systems Symposium
Design for Timing Predictability
Real-Time Systems
Virtual multiprocessor: an analyzable, high-performance architecture for real-time computing
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
DRAMsim: a memory system simulator
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
A novel instruction scratchpad memory optimization method based on concomitance metric
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
A dynamic code placement technique for scratchpad memory using postpass optimization
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
High-Performance Embedded Computing: Architectures, Applications, and Methodologies
High-Performance Embedded Computing: Architectures, Applications, and Methodologies
Bump-pointer method caching for embedded Java processors
JTRES '07 Proceedings of the 5th international workshop on Java technologies for real-time and embedded systems
RTSS '07 Proceedings of the 28th IEEE International Real-Time Systems Symposium
Toward the Predictable Integration of Real-Time COTS Based Systems
RTSS '07 Proceedings of the 28th IEEE International Real-Time Systems Symposium
Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
Impact of Cache Partitioning on Multi-tasking Real Time Embedded Systems
RTCSA '08 Proceedings of the 2008 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
Predictable programming on a precision timed architecture
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
CoMPSoC: A template for composable and predictable multi-processor system on chips
ACM Transactions on Design Automation of Electronic Systems (TODAES)
High-Performance Embedded Architecture and Compilation Roadmap
Transactions on High-Performance Embedded Architectures and Compilers I
Predictable dynamic instruction scratchpad for simultaneous multithreaded processors
Proceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecture
Memory Systems: Cache, DRAM, Disk
Memory Systems: Cache, DRAM, Disk
Hardware support for WCET analysis of hard real-time multicore systems
Proceedings of the 36th annual international symposium on Computer architecture
A real-time Java chip-multiprocessor
ACM Transactions on Embedded Computing Systems (TECS)
A dynamic instruction scratchpad memory for embedded processors managed by hardware
ARCS'11 Proceedings of the 24th international conference on Architecture of computing systems
ISORC '11 Proceedings of the 2011 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing
IA^3: An Interference Aware Allocation Algorithm for Multicore Hard Real-Time Systems
RTAS '11 Proceedings of the 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium
How to enhance a superscalar processor to provide hard real-time capable in-order SMT
ARCS'10 Proceedings of the 23rd international conference on Architecture of Computing Systems
An Analyzable Memory Controller for Hard Real-Time CMPs
IEEE Embedded Systems Letters
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Hard real-time applications in safety critical domains require high performance and time analyzability. Multi-core processors are an answer to these demands, however task interferences make multi-cores more difficult to analyze from a worst-case execution time point of view than single-core processors. We propose a multi-core SMT processor that ensures a bounded maximum delay a task can suffer due to inter-task interferences. Multiple hard real-time tasks can be executed on different cores together with additional non real-time tasks. Our evaluation shows that the proposed MERASA multi-core provides predictability for hard real-time tasks and also high performance for non hard real-time tasks.