Dynamic management of scratch-pad memory space
Proceedings of the 38th annual Design Automation Conference
Reducing energy consumption by dynamic copying of instructions onto onchip memory
Proceedings of the 15th international symposium on System Synthesis
Scratchpad memory: design alternative for cache on-chip memory in embedded systems
Proceedings of the tenth international symposium on Hardware/software codesign
WCET Centric Data Allocation to Scratchpad Memory
RTSS '05 Proceedings of the 26th IEEE International Real-Time Systems Symposium
Instruction buffering exploration for low energy embedded processors
Journal of Embedded Computing - Low-power Embedded Systems
Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison
Proceedings of the conference on Design, automation and test in Europe
Modeling the function cache for worst-case execution time analysis
Proceedings of the 44th annual Design Automation Conference
Compile-time decided instruction cache locking using worst-case execution paths
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Predator: a predictable SDRAM memory controller
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Timing predictability of cache replacement policies
Real-Time Systems
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Using Trace Scratchpads to Reduce Execution Times in Predictable Real-Time Architectures
RTAS '08 Proceedings of the 2008 IEEE Real-Time and Embedded Technology and Applications Symposium
A predictable simultaneous multithreading scheme for hard real-time
ARCS'08 Proceedings of the 21st international conference on Architecture of computing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cross-profiling for Java processors
Software—Practice & Experience
OTAWA: an open toolbox for adaptive WCET analysis
SEUS'10 Proceedings of the 8th IFIP WG 10.2 international conference on Software technologies for embedded and ubiquitous systems
A dynamic instruction scratchpad memory for embedded processors managed by hardware
ARCS'11 Proceedings of the 24th international conference on Architecture of computing systems
Temporal isolation on multiprocessing architectures
Proceedings of the 48th Design Automation Conference
How to enhance a superscalar processor to provide hard real-time capable in-order SMT
ARCS'10 Proceedings of the 23rd international conference on Architecture of Computing Systems
A hard real-time capable multi-core SMT processor
ACM Transactions on Embedded Computing Systems (TECS)
An instruction scratchpad memory allocation for the precision timed architecture
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
For precise timing analysis of hard-real applications a predictable memory system is of particular importance. Caches have a great impact on performance, but at the cost of reduced timing predictability. Conventional scratchpads, i.e. statically managed on-chip memories, provide predictable memory accesses, but they are usually badly utilized. Better memory utilization is allowed by dynamically managed scratchpads that are designed for predictability. In this paper we propose a function scratchpad that is dynamically managed in hardware and provides a predictable timing behavior. The function scratchpad exploits a simultaneous multithreaded architecture to increase the pipeline and memory bandwidth utilization while preserving predictability.