How to enhance a superscalar processor to provide hard real-time capable in-order SMT

  • Authors:

  • Jörg Mische;Irakli Guliashvili;Sascha Uhrig;Theo Ungerer

  • Affiliations:

  • Institute of Computer Science, University of Augsburg, Augsburg, Germany;Institute of Computer Science, University of Augsburg, Augsburg, Germany;Institute of Computer Science, University of Augsburg, Augsburg, Germany;Institute of Computer Science, University of Augsburg, Augsburg, Germany

  • Venue:
  • ARCS'10 Proceedings of the 23rd international conference on Architecture of Computing Systems
  • Year:
  • 2010

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Abstract

This paper describes how a superscalar in-order processor must be modified to support Simultaneous Multithreading (SMT) such that time-predictability is preserved for hard real-time applications. For superscalar in-order architectures the calculation of the Worst Case Execution Time (WCET) is much easier and tighter than for out-of-order architectures. By a careful enhancement that completely isolates the threads, this capability can be perpetuated to an in-order SMT architecture. Our design goal is to minimise the WCET of the highest priority thread, while releasing as many resources as possible for the execution of concurrent non critical threads. The resultant processor executes hard real-time threads at the same speed as its singlethreaded ancestor, but idle issue slots are dynamically used by non critical threads. The modifications to enable SMT are demonstrated by CarCore, a multithreaded embedded processor that implements the Infineon Tricore instruction set.