An in-order SMT architecture with static resource partitioning for consumer applications

Authors:
Byung In Moon;Hongil Yoon;Ilgu Yun;Sungho Kang
Affiliations:
Yonsei University, Seoul, Korea;Yonsei University, Seoul, Korea;Yonsei University, Seoul, Korea;Yonsei University, Seoul, Korea
Venue:
PDCAT'04 Proceedings of the 5th international conference on Parallel and Distributed Computing: applications and Technologies
Year:
2004

Citing 5
Cited 1

Simultaneous multithreading: maximizing on-chip parallelism

ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor

ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
ARM Architecture Reference Manual

ARM Architecture Reference Manual
The Impact of Resource Partitioning on SMT Processors

Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques
IP-address lookup using LC-tries

IEEE Journal on Selected Areas in Communications

How to enhance a superscalar processor to provide hard real-time capable in-order SMT

ARCS'10 Proceedings of the 23rd international conference on Architecture of Computing Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper proposes a simplified simultaneous multithreading (SMT) architecture aiming at CPU cores of embedded SoCs for consumer applications. This architecture reduces the hardware cost and design complexity of the SMT architecture by adopting in-order execution within threads and static resource partitioning among threads. In our architecture, processor resources are divided into three types depending on their related pipeline stages and static partitioning is applied individually to each resource type. Each thread can perform its operation using the resource partition to which it belongs. Simulation results show that reasonable static partitioning reduces the hardware cost and design complexity of SMT processors while having little negative impact on or even improving performance, compared with full resource sharing.