The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches
RTAS '08 Proceedings of the 2008 IEEE Real-Time and Embedded Technology and Applications Symposium
A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures
HPCC '09 Proceedings of the 2009 11th IEEE International Conference on High Performance Computing and Communications
Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing Analysis of Concurrent Programs Running on Shared Cache Multi-Cores
RTSS '09 Proceedings of the 2009 30th IEEE Real-Time Systems Symposium
Using Bypass to Tighten WCET Estimates for Multi-Core Processors with Shared Instruction Caches
RTSS '09 Proceedings of the 2009 30th IEEE Real-Time Systems Symposium
Modeling shared cache and bus in multi-cores for timing analysis
Proceedings of the 13th International Workshop on Software & Compilers for Embedded Systems
Back Suction: Service Guarantees for Latency-Sensitive On-chip Networks
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Worst case delay analysis for memory interference in multicore systems
Proceedings of the Conference on Design, Automation and Test in Europe
A Predictable Execution Model for COTS-Based Embedded Systems
RTAS '11 Proceedings of the 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium
Bus-Aware Multicore WCET Analysis through TDMA Offset Bounds
ECRTS '11 Proceedings of the 2011 23rd Euromicro Conference on Real-Time Systems
ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
How to enhance a superscalar processor to provide hard real-time capable in-order SMT
ARCS'10 Proceedings of the 23rd international conference on Architecture of Computing Systems
Deterministic execution model on COTS hardware
ARCS'12 Proceedings of the 25th international conference on Architecture of Computing Systems
A Unified WCET Analysis Framework for Multi-core Platforms
RTAS '12 Proceedings of the 2012 IEEE 18th Real Time and Embedded Technology and Applications Symposium
Leveraging Multi-core Computing Architectures in Avionics
EDCC '12 Proceedings of the 2012 Ninth European Dependable Computing Conference
Exact acceleration of linear object detectors
ECCV'12 Proceedings of the 12th European conference on Computer Vision - Volume Part III
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Computing Worst-Case Execution Times (WCETs) for applications executed on multi-core processors is a challenging topic since possible interferences on shared resources need to be considered. Some approaches are already proposed in literature, but the problem is still not sufficiently solved. Different approaches suffer different shortcomings. For instance, the mutual analysis of multiple applications leads to great computational complexity, pessimistic assumptions on the interference between tasks causes highly overestimated WCETs and resource privatisation dissipates processor resources. In this paper we tackle the problems of overestimated WCETs due to pessimistic analysis and differences between average-case and worst-case execution timing. We introduce a new computing paradigm for safety-critical real-time systems, which enables Quality of Service (QoS) properties to increase the utilisation of multi-core processors while still guaranteeing bounds on the worst-case behavior. This paradigm is one approach to raise multi-core performance over single-core processors, even for hard real-time systems. For evaluation we use abstractions of real applications. The concepts are implemented on Freescale's P4080 multi-core processor and AbsInt's timing analysis framework aiT. The results show an increased processor core and system utilisation of up to 99.9% and 59.3% respectively, while still providing hard deadline guarantees for all applications.