Holistic schedulability analysis for distributed hard real-time systems
Microprocessing and Microprogramming - Parallel processing in embedded real-time systems
Analysis of Cache-Related Preemption Delay in Fixed-Priority Preemptive Scheduling
IEEE Transactions on Computers
Fast and Precise WCET Prediction by Separated Cache andPath Analyses
Real-Time Systems - Special issue on worst-case execution-time analysis
Real-Time Systems: Design Principles for Distributed Embedded Applications
Real-Time Systems: Design Principles for Distributed Embedded Applications
Accurate estimation of cache-related preemption delay
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
METERG: Measurement-Based End-to-End Performance Estimation Technique in QoS-Capable Multiprocessors
RTAS '06 Proceedings of the 12th IEEE Real-Time and Embedded Technology and Applications Symposium
RTSS '07 Proceedings of the 28th IEEE International Real-Time Systems Symposium
WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches
RTAS '08 Proceedings of the 2008 IEEE Real-Time and Embedded Technology and Applications Symposium
Reliable performance analysis of a multicore multithreaded system-on-chip
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
WCET Analysis of Multi-level Non-inclusive Set-Associative Instruction Caches
RTSS '08 Proceedings of the 2008 Real-Time Systems Symposium
Hardware support for WCET analysis of hard real-time multicore systems
Proceedings of the 36th annual international symposium on Computer architecture
Timing Analysis of Concurrent Programs Running on Shared Cache Multi-Cores
RTSS '09 Proceedings of the 2009 30th IEEE Real-Time Systems Symposium
Using Bypass to Tighten WCET Estimates for Multi-Core Processors with Shared Instruction Caches
RTSS '09 Proceedings of the 2009 30th IEEE Real-Time Systems Symposium
Static bus schedule aware scratchpad allocation in multiprocessors
Proceedings of the 2011 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
Deterministic execution model on COTS hardware
ARCS'12 Proceedings of the 25th international conference on Architecture of Computing Systems
Static task partitioning for locked caches in multi-core real-time systems
Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems
Memory-centric scheduling for multicore hard real-time systems
Real-Time Systems
Predictable two-level bus arbitration for heterogeneous task sets
ARCS'13 Proceedings of the 26th international conference on Architecture of Computing Systems
Quality of service capabilities for hard real-time applications on multi-core processors
Proceedings of the 21st International conference on Real-Time Networks and Systems
Proceedings of the 21st International conference on Real-Time Networks and Systems
Building timing predictable embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
A Unified WCET analysis framework for multicore platforms
ACM Transactions on Embedded Computing Systems (TECS)
WCET analysis with MRU cache: Challenging LRU for predictability
ACM Transactions on Embedded Computing Systems (TECS)
Static analysis of multi-core TDMA resource arbitration delays
Real-Time Systems
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Timing analysis of concurrent programs running on multi-core platforms is currently an important problem. The key to solving this problem is to accurately model the timing effects of shared resources in multi-cores, namely shared cache and bus. In this paper, we provide an integrated timing analysis framework that captures timing effects of both shared cache and shared bus. We also develop a cycle-accurate simulation infra-structure to evaluate the precision of our analysis. Experimental results from a large fragment of an in-orbit spacecraft software show that our analysis produces around 20% over-estimation over simulation results.