A bridging model for parallel computation
Communications of the ACM
Transactional memory: architectural support for lock-free data structures
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Performance analysis of embedded software using implicit path enumeration
LCTES '95 Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems
Timing Anomalies in Dynamically Scheduled Microprocessors
RTSS '99 Proceedings of the 20th IEEE Real-Time Systems Symposium
Preemptible Atomic Regions for Real-Time Java
RTSS '05 Proceedings of the 26th IEEE International Real-Time Systems Symposium
Automatic Derivation of Loop Bounds and Infeasible Paths for WCET Analysis Using Abstract Execution
RTSS '06 Proceedings of the 27th IEEE International Real-Time Systems Symposium
A Scalable, Non-blocking Approach to Transactional Memory
HPCA '07 Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
CoMPSoC: A template for composable and predictable multi-processor system on chips
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Real-Time Support for Software Transactional Memory
RTCSA '09 Proceedings of the 2009 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
RTTM: real-time transactional memory
Proceedings of the 2010 ACM Symposium on Applied Computing
Modeling shared cache and bus in multi-cores for timing analysis
Proceedings of the 13th International Workshop on Software & Compilers for Embedded Systems
ISORC '10 Proceedings of the 2010 13th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing
Transactional Memory, 2nd Edition
Transactional Memory, 2nd Edition
Proceedings of the Conference on Design, Automation and Test in Europe
Design and Implementation of Real-Time Transactional Memory
FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
Partial flow analysis with oRange
ISoLA'10 Proceedings of the 4th international conference on Leveraging applications of formal methods, verification, and validation - Volume Part II
Deadline-aware scheduling for Software Transactional Memory
DSN '11 Proceedings of the 2011 IEEE/IFIP 41st International Conference on Dependable Systems&Networks
Transactional memory for dependable embedded systems
DSNW '11 Proceedings of the 2011 IEEE/IFIP 41st International Conference on Dependable Systems and Networks Workshops
Software Transactional Memory as a Building Block for Parallel Embedded Real-Time Systems
SEAA '11 Proceedings of the 2011 37th EUROMICRO Conference on Software Engineering and Advanced Applications
Deterministic execution model on COTS hardware
ARCS'12 Proceedings of the 25th international conference on Architecture of Computing Systems
IEEE Embedded Systems Letters
STM concurrency control for embedded real-time software with tighter time bounds
Proceedings of the 49th Annual Design Automation Conference
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In this paper, we utilise transactional memory (TM) to limit interferences of concurrent hard real-time (HRT) and best-effort (BE) tasks in a shared memory multi-core. We first propose a way to calculate the worst-case execution time (WCET) bound of HRT transactions when the set of concurrent transactions is known. In the next step we enhance our TM contention manager to prioritise transactions depending on their real-time requirements. With our approach it is possible to bound the interferences of any BE transaction and thus ensure a predictable execution of concurrently running HRT transactions. Our evaluation shows that the impact of BE tasks on the WCET bound of HRT tasks is minimal, while allowing them to share data.