Transactional memory: architectural support for lock-free data structures
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
An architecture for mostly functional languages
LFP '86 Proceedings of the 1986 ACM conference on LISP and functional programming
The Real-Time Specification for Java
The Real-Time Specification for Java
Cache Behavior Prediction by Abstract Interpretation
SAS '96 Proceedings of the Third International Symposium on Static Analysis
Software transactional memory for dynamic-sized data structures
Proceedings of the twenty-second annual symposium on Principles of distributed computing
Real-Time Distributed Object Computing: Ready for Mission-Critical Embedded System Applications
DOA '01 Proceedings of the Third International Symposium on Distributed Objects and Applications
Language support for lightweight transactions
OOPSLA '03 Proceedings of the 18th annual ACM SIGPLAN conference on Object-oriented programing, systems, languages, and applications
Transactional Memory Coherence and Consistency
Proceedings of the 31st annual international symposium on Computer architecture
Programming with transactional coherence and consistency (TCC)
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Parameterized object sensitivity for points-to analysis for Java
ACM Transactions on Software Engineering and Methodology (TOSEM)
Preemptible Atomic Regions for Real-Time Java
RTSS '05 Proceedings of the 26th IEEE International Real-Time Systems Symposium
Effective static race detection for Java
Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation
Refinement-based context-sensitive points-to analysis for Java
Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation
Architectural Support for Software Transactional Memory
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
A Java processor architecture for embedded real-time systems
Journal of Systems Architecture: the EUROMICRO Journal
Time-predictable computer architecture
EURASIP Journal on Embedded Systems - FPGA supercomputing platforms, architectures, and techniques for accelerating computationally complex algorithms
The Art of Multiprocessor Programming
The Art of Multiprocessor Programming
A real-time Java chip-multiprocessor
ACM Transactions on Embedded Computing Systems (TECS)
Real-time wait-free queues using micro-transactions
Proceedings of the 9th International Workshop on Java Technologies for Real-Time and Embedded Systems
STM concurrency control for embedded real-time software with tighter time bounds
Proceedings of the 49th Annual Design Automation Conference
STM concurrency control for multicore embedded real-time software: time bounds and tradeoffs
Proceedings of the 27th Annual ACM Symposium on Applied Computing
About 15 years of real-time Java
Proceedings of the 10th International Workshop on Java Technologies for Real-time and Embedded Systems
Worst case response time for real-time software transactional memory
Proceedings of the 2012 ACM Research in Applied Computation Symposium
Data cache organization for accurate timing analysis
Real-Time Systems
Revisiting transactions in Ada
ACM SIGAda Ada Letters
Proceedings of the 21st International conference on Real-Time Networks and Systems
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Hardware transactional memory is a promising synchronization technology for chip-multiprocessors. It simplifies programming of concurrent applications and allows for higher concurrency than lock based synchronization. Standard transactional memory is optimized for average case throughput, but for real-time systems we are interested in worst-case execution times. We propose real-time transactional memory (RTTM) as a time-predictable synchronization solution for chip-multiprocessors in real-time systems. We define the hardware for time-predictable transactions and provide a bound for the maximum transaction retries. The proposed RTTM is evaluated with a simulation of a Java chip-multiprocessor.