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Transactional memory: architectural support for lock-free data structures
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ARB: A Hardware Mechanism for Dynamic Reordering of Memory References
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Transaction Processing: Concepts and Techniques
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Starfire: Extending the SMP Envelope
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A low-overhead coherence solution for multiprocessors with private cache memories
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Token coherence: decoupling performance and correctness
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The Jrpm system for dynamically parallelizing Java programs
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Partially ordered epochs for thread-level speculation
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TAPE: a transactional application profiling environment
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Unbounded page-based transactional memory
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Store Atomicity for Transactional Memory
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Ased: availability, security, and debugging support usingtransactional memory
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TxLinux and MetaTM: transactional memory and the operating system
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ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Flexible Decoupled Transactional Memory Support
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Rerun: Exploiting Episodes for Lightweight Memory Race Recording
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Atom-Aid: Detecting and Surviving Atomicity Violations
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Software transactional memory: why is it only a research toy?
Communications of the ACM - Remembering Jim Gray
CAR-STM: scheduling-based collision avoidance and resolution for software transactional memory
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ACM SIGPLAN Notices
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Mechanical Verification of Transactional Memories with Non-transactional Memory Accesses
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Bristlecone: A Language for Robust Software Systems
ECOOP '08 Proceedings of the 22nd European conference on Object-Oriented Programming
Software Transactional Memory: Why Is It Only a Research Toy?
Queue - The Concurrency Problem
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An efficient transactional memory algorithm for computing minimum spanning forest of sparse graphs
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xCalls: safe I/O in memory transactions
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Dependence-aware transactional memory for increased concurrency
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Verification of chip multiprocessor memory systems using a relaxed scoreboard
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Access Control and Information Flow in Transactional Memory
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A memory system design framework: creating smart memories
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Dynamic performance tuning for speculative threads
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A Domain Specific Language for Composable Memory Transactions in Java
DSL '09 Proceedings of the IFIP TC 2 Working Conference on Domain-Specific Languages
NZTM: nonblocking zero-indirection transactional memory
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The Bulk Multicore architecture for improved programmability
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NePaLTM: Design and Implementation of Nested Parallelism for Transactional Memory Systems
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SPMTM: A Novel ScratchPad Memory Based Hybrid Nested Transactional Memory Framework
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81.6 GOPS object recognition processor based on a memory-centric NoC
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-chip transactional memory system for FPGAs using TCC model
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EazyHTM: eager-lazy hardware transactional memory
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Brief Announcement: Relay: A Cache-Coherence Protocol for Distributed Transactional Memory
OPODIS '09 Proceedings of the 13th International Conference on Principles of Distributed Systems
LIRAC: using live range information to optimize memory access
ARCS'07 Proceedings of the 20th international conference on Architecture of computing systems
RTTM: real-time transactional memory
Proceedings of the 2010 ACM Symposium on Applied Computing
The multicore revolution: the challenges for theory
FSTTCS'07 Proceedings of the 27th international conference on Foundations of software technology and theoretical computer science
Exploring data reusing of failed transaction
APPT'07 Proceedings of the 7th international conference on Advanced parallel processing technologies
Directory-based conflict detection in hardware transactional memory
HiPC'08 Proceedings of the 15th international conference on High performance computing
DRFX: a simple and efficient memory model for concurrent programming languages
PLDI '10 Proceedings of the 2010 ACM SIGPLAN conference on Programming language design and implementation
Making nested parallel transactions practical using lightweight hardware support
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Timetraveler: exploiting acyclic races for optimizing memory race recording
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Modeling critical sections in Amdahl's law and its implications for multicore design
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Extensible software transactional memory
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Evaluation of a hardware transactional memory model in an NoC-based embedded MPSoC
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Scalable hardware support for conditional parallelization
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LV*: a class of lazy versioning HTMs for low-cost integration of transactional memory systems
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ScalableBulk: Scalable Cache Coherence for Atomic Blocks in a Lazy Environment
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Hardware Support for Relaxed Concurrency Control in Transactional Memory
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
A Dynamically Adaptable Hardware Transactional Memory
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ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory
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The ZCache: Decoupling Ways and Associativity
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Runtime parallelization of legacy code on a transactional memory system
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RMS-TM: a comprehensive benchmark suite for transactional memory systems
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Efficient partial roll-backing mechanism for transactional memory systems
Transactions on high-performance embedded architectures and compilers III
A case for an SC-preserving compiler
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Transactional conflict decoupling and value prediction
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Multiset signatures for transactional memory
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ZEBRA: a data-centric, hybrid-policy hardware transactional memory design
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Vantage: scalable and efficient fine-grain cache partitioning
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Real-time wait-free queues using micro-transactions
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Sniper: exploring the level of abstraction for scalable and accurate parallel multi-core simulation
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Compiler support for concurrency synchronization
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FlexSig: Implementing flexible hardware signatures
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Hardware transactional memory with software-defined conflicts
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Conflict detection and validation strategies for software transactional memory
DISC'06 Proceedings of the 20th international conference on Distributed Computing
DISC'06 Proceedings of the 20th international conference on Distributed Computing
Reducing false aborts in STM systems
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
Applying transactional memory to concurrency bugs
ASPLOS XVII Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems
Efficient sequential consistency via conflict ordering
ASPLOS XVII Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems
Distributed transactional memory for metric-space networks
DISC'05 Proceedings of the 19th international conference on Distributed Computing
Improving performance by reducing aborts in hardware transactional memory
HiPEAC'10 Proceedings of the 5th international conference on High Performance Embedded Architectures and Compilers
Efficient transaction nesting in hardware transactional memory
ARCS'10 Proceedings of the 23rd international conference on Architecture of Computing Systems
Runtime automatic speculative parallelization
CGO '11 Proceedings of the 9th Annual IEEE/ACM International Symposium on Code Generation and Optimization
SnCTM: reducing false transaction aborts by adaptively changing the source of conflict detection
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Compiler support for fine-grain software-only checkpointing
CC'12 Proceedings of the 21st international conference on Compiler Construction
Hardware support for enforcing isolation in lock-based parallel programs
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Delegation and nesting in best-effort hardware transactional memory
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End-to-end sequential consistency
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BlockChop: dynamic squash elimination for hybrid processor architecture
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Monitoring data structures using hardware transactional memory
RV'11 Proceedings of the Second international conference on Runtime verification
Transactional prefetching: narrowing the window of contention in hardware transactional memory
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SC '12 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
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SC '12 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
Starvation-free transactional memory-system protocols
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Support for fine-grained synchronization in shared-memory multiprocessors
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Implicit transactional memory in kilo-instruction multiprocessors
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An integrated pseudo-associativity and relaxed-order approach to hardware transactional memory
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TSO_ATOMICITY: efficient hardware primitive for TSO-preserving region optimizations
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Conversion: multi-version concurrency control for main memory segments
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Future Generation Computer Systems
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In this paper, we propos a new shared memory model: Transactionalmemory Coherence and Consistency (TCC).TCC providesa model in which atomic transactions are always the basicunit of parallel work, communication, memory coherence, andmemory reference consistency.TCC greatly simplifies parallelsoftware by eliminating the need for synchronization using conventionallocks and semaphores, along with their complexities.TCC hardware must combine all writes from each transaction regionin a program into a single packet and broadcast this packetto the permanent shared memory state atomically as a large block.This simplifies the coherence hardware because it reduces theneed for small, low-latency messages and completely eliminatesthe need for conventional snoopy cache coherence protocols, asmultiple speculatively written versions of a cache line may safelycoexist within the system.Meanwhile, automatic, hardware-controlledrollback of speculative transactions resolves any correctnessviolations that may occur when several processors attemptto read and write the same data simultaneously.The cost of thissimplified scheme is higher interprocessor bandwidth.To explore the costs and benefits of TCC, we study the characterisitcsof an optimal transaction-based memory system, and examinehow different design parameters could affect the performanceof real systems.Across a spectrum of applications, the TCC modelitself did not limit available parallelism.Most applications areeasily divided into transactions requiring only small write buffers,on the order of 4-8 KB.The broadcast requirements of TCCare high, but are well within the capabilities of CMPs and small-scaleSMPs with high-speed interconnects.